1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a clock forwarding circuit in a semiconductor integrated circuit and a clock forwarding method.
2. Description of the Related Art
There are many individual circuits or blocks in an overall semiconductor integrated circuit. Data sending and receiving are carried out among the many blocks. In order to send and receive data, a data line and a clock line are connected between a data send port, i.e., a block for sending data, and a data receive port, i.e., a block for receiving data. However, the data line and the clock line present a load to the associated circuitry which depends on the length, thickness and shape of their conductors. Accordingly, when data and clock signals are transmitted respectively through the data and clock lines, interconnection delay occurs. In particular, when the interconnection delay time on the data line approaches or exceeds the period of a clock input to the data send port and data receive port, malfunction in the form of data errors may occur when data output from the data send port is transmitted to the data receive port through the data line. To prevent this, clock forwarding techniques are used to transmit data from the data send port to the data receive port without having to increase the period of the clock.
FIG. 1 shows a schematic block diagram of a prior art clock forwarding circuit 100. Referring to FIG. 1, the conventional clock forwarding circuit 100 includes a data sending latch 101, a clock sending latch 103, a data driver 105, a clock driver 107, a data line 109, a clock line 111, a clock generator 113, a first data receiving latch 115, a second data receiving latch 117, a selector 119, a third data receiving latch 121 and an unload control circuit 123. The data sending latch 101 and the clock sending latch 103 are included in a data receive port 102; and the clock generator 113, the first, second and third data receiving latches 115, 117 and 121, the selector 119 and the unload control circuit 123 are included in a data receive port 104.
In the prior art circuit of FIG. 1, the data being sent, in the form of a signal DATA, is applied to the data input line of the data sending latch 101; and the clock signal SCLK is applied to the clock inputs of the data sending latch 101 and the clock sending latch 103. The SCLK signal causes the DATA applied to latch 101 to appear at the Q output of latch 101. The SCLK signal is also frequency divided by latch 103 and appears at half its original frequency at the Q output of latch 103. The data signal is driven across data line 109 by data driver 105, and the frequency-divided SCLK signal is driven across clock line 111 by clock driver 107.
At the data receive port 104, the data signal on the data line 109 is applied to the data inputs of the two data receiving latches 115 and 117. The clock generator circuit 113 receives the frequency-divided SCLK signal and sends an in-phase version of the divided signal to the clock input of latch 115 and an inverted version of the clock signal to the clock input of latch 117. The latches 115 and 117 serve to restore the original clock frequency of the SCLK signal. Assuming that the latches 115 and 117 are forward-edge triggered, on the forward edge of the divided signal, the data is clocked through latch 115 to the selector 119. On the negative-going edge of the clock signal, data is clocked through latch 117 to the selector 119.
The unload control circuit 123 is used to control the selector 119 to select one of the data outputs from latch 115 or 117 in response to a target clock signal TCLK. The selected output is forwarded to the data input of the third data receive latch 121 in accordance with the timing of the TCLK signal. On the positive-going edge of the TCLK signal, the data selected by selector 119 appears at the Q output of latch 121 as the RDATA signal.
In the conventional clock forwarding circuit 100, interconnection delay time occurring on the data line 109 must be almost the same as interconnection delay time occurring on the clock line 111. Thus, the conductor of the data line 109 and the conductor of the clock line 111 must be designed and manufactured to have the same load. This places a very serious restriction on the design of the overall circuit, since the data line 109 and clock line 111 need to be designed to have the same length and thickness and must have similar proximal circuitry such that reactive impedances are similar.
In the conventional clock forwarding circuit 100, when the load of the data line 109 is different from that of the clock line 111, the interconnection delay of the data line 109 becomes different from the interconnection delay of the clock line 111. This reduces an operation timing margin of the data receive port 104. The clock signal SCLK is continuously generated and supplied to the data receive port 104 via the clock line 111 to synchronize data transfer. This tends to increase power consumption of the circuit.